memory bus
英 [ˈmeməri bʌs]
美 [ˈmeməri bʌs]
网络 内存总线; 存储器总线; 存储总线; 记忆汇流排; 记忆体汇流排
双语例句
- NUMA reduces the contention for a system's shared memory bus by having more memory buses and fewer processors on each bus.
NUMA通过在每个总线使用更多内存总线和更少处理器来减少系统共享内存总线的争用。 - Typically even on an old and slow piece of hardware, the CPU, memory, and BUS components are fast enough to match up with the insertion.
一般即使旧的较慢的硬件平台上，CPU、内存和BUS组件都足以支撑插入操作。 - The processor is connected to physical memory by the memory bus.
处理器通过内存总线连接到物理内存。 - This stage makes heavy use of the video memory and the video memory bus. Due to the complex in the hydrolyze process, the inorganic flocculant does a obvious influence on the result of Coagu-flocculation in industry.
这个过程中对显存和显存总线的负担比较大。无机混凝剂由于其水解过程的复杂性，在工业使用中对混凝的效果有较明显的影响。 - The irredundant sorting bus encoding method reduces the power dissipation of highly capacitive memory address bus based on the dynamic reordering of the modified offset address bus lines.
提出了一种新的低功耗非冗余排序总线编码方法，通过对改进的偏移地址线的动态重排以降低具有高负载的地址总线的功耗。 - A novel adaptive-offset bus encoding method was presented for reducing the power dissipation of highly capacitive memory address bus.
为了降低大负载地址总线的功耗，提出了一种新的低功耗自适应偏移量总线编码方法。 - The dual-ported RAM is a kind of special memory, and the bus data share between double high-speed microprocessors is carried out by using it.
双端口RAM是一种特殊的数据存储芯片，利用双端口RAM可以实现双高速单片机总线方式的数据共享。 - Memory the bus of the serial interface is equipped with data flash, EEPROM& ferroelectric chip.
串口总线上配备数据存储器，EEPROM及铁电芯片。 - The AD/ DA conversion, DMA transmission, system memory allocation and USB bus interface accessing are introduced.
系统硬件部分着重介绍了AD／DA数模、模数转换，语音DMA传输，存储器配置，USB总线接口访问等部分。 - Based on the real-time constrain of the multimedia stream and the disk data stream model, the relationship between the performances and the online storage subsystem in video on demand was presented quantitatively with the analysis of memory and interface bus.
基于多媒体流实时播放的特性和磁盘数据流模型的研究，进一步分析了内存和接口总线的特性，提出了视频点播（VoD）系统性能指标与在线存储系统之间的定量关系。 - The data acquisition result is sent to PC memory through ISA bus.
数据采集结果通过ISA总线送PC机内存。 - A Shared Memory Mechanism Based on Bus for Multi processor
一种基于总线的多处理器共享内存机制 - Technology of Share Memory Based on CPCI Bus
基于CPCI总线的共享内存技术的实现 - Multi-channels data recorder with huge-capacity memory based on PC bus
基于PC总线的海量多路波形数据记录仪 - Applying In-System Reprogrammability in a REFLECTIVE MEMORY Bus Controller
在线可编程逻辑器件在反射存储器总线控制器设计中的应用 - Design of high performance I/ O interface based on memory bus
基于内存总线的高性能I/O接口设计 - A design idea which converts the memory bus to a local bus for system peripheral interconnection is presented in this paper.
提出了将内存总线扩展为面向系统外部设备互连的局部总线的设计概念。 - Physical shared memory bus, message translating LAN and copy shared memory network are the main interconnecting technology using in distributed real-time simulation.
分布式仿真系统可采用的联接方式主要有物理共享内存总线、消息传递网络和复制共享内存网络三种。 - In the hardware design, we discuss the connecting of A/ D, memory expansion, bus control, and program boot loader.
硬件设计讨论了基于TI公司的TMS320C31的设计，包括A／D的连接，存储器的扩展，总线的控制，以及程序引导装入功能的实现。 - Off-chip memory latency is mainly determined by DRAM latency, and memory bandwidth is determined by data transfer rate through the memory bus.
片外存储系统的访存延迟主要由DRAM延迟决定，带宽则是由内存总线的数据传输率所决定。 - The results show that the whole effective memory bandwidth of multiple bus multiprocessor systems isn't affected by the priority hierarchy.
结果表明：优先级并不影响整个系统的有效带宽性能。 - The main control layer includes interfaces such as memory, CAN bus, Ethernet, LCD, touch screen and motor drive circuit, etc. The head control layer includes solenoid drive circuit, needle selector drive circuit, stepper motor drive circuit.
其中主控制层部分包括存储器电路、CAN总线电路、以太网、LCD与触摸屏电路、电机驱动电路等，机头控制层包括电磁铁驱动、选针器驱动、步进电机驱动电路等。 - Each processor accesses to exterior memory by the shared bus.
各处理器通过共享总线访问外部存储器。 - To enhance the available cycle utilization efficiency of memory data bus, we propose a stream application oriented memory scheduling mechanism.
为了提高主存数据总线的有效周期利用率，提出了一种面向流应用的存储调度机制。 - The transplantation of such software to cellphone platform would be limited by factors as operation speed of cellphone, memory space and bus bandwidth.
若要将此类软件移植到手机平台上，将要受到手机运算速度、存储空间量和总线带宽等因素的限制。 - Using phase lock loop technique based on FPGA, produce pixel clock technology to design collection system logic control and ADC and external memory and PCI bus between controller of sequential coordinate work.
采用锁相环技术产生象素时钟，采用FPGA技术来设计采集系统的逻辑控制和ADC、外部存储器以及PCI总线控制器之间的时序协调工作。